1. Field of the Invention
The present invention relates to the field of integrated circuits and, more particularly, to a network processor implemented using an integrated circuit (IC) having programmable logic and programmable interconnects.
2. Description of the Related Art
Electronic circuit designs can be constructed, simulated, debugged, and translated into electronic hardware using a High Level Modeling System (HLMS). Typically, an HLMS is implemented as a software-based design tool which provides blocks that can be combined to build a circuit design. A block refers to a high level software construct which represents a particular circuit function, such as multiplexing, addition, multiplication, or the like. The blocks can be arranged within the HLMS to form a circuit and/or system. Communication among the blocks can be represented by wires, or signals, which graphically link the blocks. Once configured, the HLMS can run various simulations upon the design. The HLMS further can generate a hardware implementation from the block representation of the circuit design. For example, an HLMS can generate the bitstream necessary to program a field programmable gate array (FPGA) or can generate hardware description language (HDL) files necessary to specify the hardware design.
One example of an HLMS is System Generator™, available from Xilinx, Inc. of San Jose, Calif. System Generator™ is a system level modeling tool that facilitates FPGA hardware design. System Generator™ can function with other design tools to provide a modeling environment that is well suited to hardware design. The System Generator™ tool provides high level abstractions, i.e., blocks, which can be automatically compiled into an FPGA. In addition, access to underlying FPGA resources can be provided through low level block abstractions which facilitate the construction of highly efficient FPGA designs.
It is possible to incorporate circuit designs, which already have been implemented in hardware, back into the HLMS development environment. To do so, a high bandwidth communication channel must be established between the computer system hosting the HLMS and the device under test (DUT). The DUT typically is a design implemented within a programmable logic device (PLD) such as an FPGA. The PLD is installed on a hardware platform which is coupled to the host computer system via the high bandwidth communication link. The process of running a simulation involving a hardware platform and a software platform working cooperatively with one another is referred to as hardware co-simulation. One variety of hardware co-simulation interface that provides a high-bandwidth link between the host computer system and the hardware platform is a point-to-point Ethernet connection. With point-to-point Ethernet hardware co-simulation, low-level Ethernet frames are transmitted between the host computer system and the hardware platform.
Network processors often are used with network specific applications to increase the efficiency of the network. A network processor typically is implemented as a software-controlled integrated circuit which has been optimized for use in applications involving network routing and packet processing. While there is no standard architecture, many network processors feature complex architectures having multiple CPU's running in parallel. In such a configuration, one CPU usually receives and handles network control packets while the other CPU's pass data packets through the system at network speeds. In any case, a network processor can perform functions such as packet classification, traffic shaping, queuing, and the like.
It would be beneficial to minimize the size and complexity of a network processor such that the network processor can be implemented on a PLD while conserving available PLD resources.